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ltc2451 1 2451fg typical application features description ultra-tiny, 16-bit ? adc with i 2 c interface the ltc ? 2451 is an ultra-tiny, 16-bit, analog-to-digital converter. the ltc2451 uses a single 2.7v to 5.5v sup - ply, accepts a single-ended analog input voltage and communicates through an i 2 c interface. the converter is available in an 8-pin, 3mm 2mm dfn or tsot-23 package. it includes an integrated oscillator that does not require any external components. it uses a delta-sigma modulator as a converter core and provides single-cycle settling time for multiplexed applications. the ltc2451 includes a proprietary input sampling scheme that re - duces the average input sampling current several orders of magnitude lower than conventional ? converters. the ltc2451 is capable of up to 60 conversions per second and, due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. in the 30hz mode, the ltc2451 includes continuous internal offset calibration algorithms which are transparent to the user, ensuring accur acy over time and over the operating temperature range. the converter has external ref + and ref C pins and the input voltage can range from v ref C to v ref + . if v ref + = v cc and v ref C = gnd, the input voltage can range from gnd to v cc . following a single conversion, the ltc2451 can auto - matically enter sleep mode and reduce its power to less than 0.2a. if the user reads the adc once per second, the ltc2451 consumes an average of less than 50w from a 2.7v supply. n gnd to v cc single-ended input range n 0.02lsb rms noise n 2lsb inl, no missing codes n 1lsb offset error n 4lsb full-scale error n programmable 30/60 conversions per second n single conversion settling time for multiplexed applications n single-cycle operation with auto shutdown n 400a supply current n 0.2a sleep current n internal oscillatorno external components required n single supply, 2.7v to 5.5v operation n 2-wire i 2 c interface n ultra-tiny 3mm 2mm dfn or tsot-23 package applications n system monitoring n environmental monitoring n direct temperature measurements n instrumentation n industrial process control n data acquisition n embedded adc upgrades integral nonlinearity, v cc = 3v sensor scl 2-wire i 2 c interface sda 0.1 f 10f 2.7v to 5.5v 1k in ref + v cc ref ? gnd ltc2451 2451 ta01a 0.1 f input voltage (v) 0 ?3 inl (lsb) ?2 ?1 0 1 3 0.5 1 1.5 2 2451 ta01b 2.5 3 2 t a = ? 45c, 25c t a = 90c l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6208279, 6411242, 7088280, 7164378.
ltc2451 2 2451fg pin configuration absolute maximum ratings supply voltage (v cc ) ................................... C0.3v to 6v analog input voltage (v in ) ............ C0.3v to (v cc + 0.3v) reference voltage (v ref + , v ref C ) ... C0.3v to (v cc + 0.3v) digital voltage (v sda , v scl ) .......... C0.3v to (v cc + 0.3v) (notes 1, 2) top view 9 ddb package 8-lead (3mm 2mm) plastic dfn 5 6 7 8 4 3 2 1 gnd ref ? ref + v cc sda scl in gnd c/i grade t jmax = 125c, ja = 76c/w exposed pad (pin 9) is gnd, must be soldered to pcb gnd 1 ref ? 2 ref + 3 v cc 4 8 sda 7 scl 6 in 5 gnd top view ts8 package 8-lead plastic tsot-23 c/i grade t jmax = 125c, ja = 140c/w order information electrical characteristics parameter conditions min typ max units resolution (no missing codes) (note 3) l 16 bits integral nonlinearity (note 4) l 2 10 lsb offset error 30hz mode l 0.08 0.5 mv offset error 60hz mode l 0.5 2 mv offset error drift 0.02 lsb/c gain error l 0.01 0.02 % of fs gain error drift 0.02 lsb/c transition noise 1.4 v rms power supply rejection dc 30hz mode 80 db power supply rejection dc 60hz mode 80 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc2451cddb#trmpbf ltc2451cddb#trpbf ldgq 8-lead plastic (3mm 2mm) dfn 0c to 70c ltc2451iddb#trmpbf ltc2451iddb#trpbf ldgq 8-lead plastic (3mm 2mm) dfn C40c to 85c ltc2451cts8#trmpbf ltc2451cts8#trpbf ltdns 8-lead plastic tsot-23 0c to 70c ltc2451its8#trmpbf ltc2451its8#trpbf ltdns 8-lead plastic tsot-23 C40c to 85c trm = 500 pieces. *temperature grades are identifed by a label on the shipping container. consult ltc marketing for parts specifed with wider operating temperature ranges. consult ltc marketing for information on lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ storage temperature range ................... C65c to 150c operating temperature range ltc2451c ................................................ 0c to 70c ltc2451i .............................................. C40c to 85c
ltc2451 3 2451fg the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 2.7v to 5.5v. (notes 2, 7) symbol parameter conditions min typ max units t conv conversion time 30hz mode l 26 33.2 46 ms t conv conversion time 60hz mode l 13 16.6 23 ms f scl scl clock frequency l 0 400 khz t hd(sda) hold time (repeated) start condition l 0.6 s t low low period of the scl pin l 1.3 s t high high period of the scl pin l 0.6 s t su(sta) set-up time for a repeated start condition l 0.6 s t hd(dat) data hold time l 0 0.9 s t su(dat) data set-up time l 100 ns t r rise time for sda/scl signals (note 6) l 20 + 0.1c b 300 ns t f fall time for sda/scl signals (note 6) l 20 + 0.1c b 300 ns t su(sto) set-up time for stop condition l 0.6 s t buf bus free time between a stop and start condition l 1.3 s i 2 c timing characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 2.7v to 5.5v. (note 2) analog input and references the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion sleep l l 400 0.2 700 0.5 a a power requirements the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 2) symbol parameter conditions min typ max units v ih high level input voltage l 0.7v cc v v il low level input voltage l 0.3v cc v v hys hysteresis of schmidt trigger inputs (note 3) l 0.05v cc v v ol low level output voltage (sda) i = 3ma l 0.4 v i in input leakage 0.1v cc v in 0.9v cc l C1 1 a c i capacitance for each i/o pin l 10 pf c b capacitance load for each bus line l 400 pf i 2 c inputs and outputs symbol parameter conditions min typ max units v in input voltage range l v ref C v ref + v v ref + positive reference voltage range v ref + C v ref C 2.5v l v cc C 2.5 v cc v v ref C negative reference voltage range v ref + C v ref C 2.5v l 0 v cc C 2.5 v c in in sampling capacitance 0.35 pf i dc_leak(vin) in dc leakage current v in = gnd (note 8) v in = v cc (note 8) l l C10 C10 1 1 10 10 na na i dc_leak(ref + , ref C ) ref + , ref C dc leakage current v ref = 5v (note 8) l C10 1 10 na i conv input sampling current (note 5) 50 na
ltc2451 4 2451fg integral nonlinearity v cc = v ref + = 5v integral nonlinearity v cc = 5v, v ref + = 3v integral nonlinearity v cc = v ref + = 3v the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (notes 2, 7) i 2 c timing characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. all voltage values are with respect to gnd. v cc = 2.7v to 5.5v, unless otherwise specifed. specifcations apply to both 30hz and 60hz modes unless otherwise specifed. v ref = v ref + C v ref C , v refcm = (v ref + + v ref C )/2, fs = v ref + C v ref C ; v ref C v in v ref + note 3. guaranteed by design, not subject to test. note 4. integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. guaranteed by design, test correlation and 3-point transfer curve measurement. note 5. input sampling current is the average input current drawn from the input sampling network while the ltc2451 is actively sampling the input. c b = capacitance of one bus line in pf. note 6. c b = capacitance of one bus line in pf. note 7. all values refer to v ih(min ) and v il(max) levels. note 8. a positive current is fowing into the dut pin. symbol parameter conditions min typ max units t of output fall time v ih(min) to v il(max) bus load c b 10pf to 400pf (note 6) l 20 + 0.1c b 250 ns t sp input spike suppression l 50 ns typical performance characteristics t a = 25c; graphs apply to both 30hz and 60hz modes, unless otherwise noted. input voltage (v) 0 ?3 inl (lsb) ?2 ?1 0 1 3 1 2 3 4 2451 g01 5 2 t a = ? 45c, 25c, 90c input voltage (v) 0 ?3 inl (lsb) ?2 ?1 0 1 3 0.5 1 1.5 2 2451 g02 2.5 3 2 t a = ? 45c, 25c, 90c input voltage (v) 0 ?3 inl (lsb) ?2 ?1 0 1 3 0.5 1 1.5 2 2451 g03 2.5 3 2 t a = ? 45c, 25c t a = 90c
ltc2451 5 2451fg maximum inl vs temperature offset error vs temperature 30hz mode offset error vs temperature 60hz mode gain error vs temperature transition noise vs temperature transition noise vs output code temperature (c) ?50 0 inl (lsb) 1.0 2.0 3.0 ?25 0 25 50 75 4.0 5.0 0.5 1.5 2.5 3.5 4.5 100 2451 g04 v cc = 3v v cc = 5v v cc = 4.1v temperature (c) ?50 0.00 offset (mv) 0.10 0.20 0.30 ?25 0 25 50 75 0.40 0.50 0.05 0.15 0.25 0.35 0.45 100 2451 g05 v cc = 3v v cc = 4.1v v cc = 5v temperature (c) ?50 0.00 offset (mv) 0.10 0.20 0.30 ?25 0 25 50 75 0.40 0.50 0.05 0.15 0.25 0.35 0.45 100 2451 g06 v cc = 5v, 4.1v, 3v temperature (c) ?50 0 gain error (lsb) 2 4 6 ?25 0 25 50 75 8 10 1 3 5 7 9 100 2451 g07 v cc = 3v v cc = 4.1v v cc = 5v temperature (c) ?50 0 transition noise rms (v) 0.5 1.0 1.5 2.0 3.0 ?25 0 25 50 2451 g08 75 100 2.5 v cc = 5v v cc = 3v output code 0 65536 0 transition noise rms (v) 0.5 1.0 1.5 2.0 16384 49152 32768 2451 g09 2.5 3.0 v cc = 5v v cc = 3v typical performance characteristics t a = 25c; graphs apply to both 30hz and 60hz modes, unless otherwise noted. conversion mode power supply current vs temperature sleep mode power supply current vs temperature average power dissipation vs temperature v cc = 3v, 30hz mode temperature (c) 0 conversion current (a) 100 200 300 400 2451 g10 500 600 ?50 ?25 0 25 50 75 100 v cc = 5v v cc = 3v v cc = 4.1v temperature (c) ?50 0 sleep current (na) 50 100 150 200 250 ?25 0 25 50 2451 g11 75 100 v cc = 5v v cc = 3v v cc = 4.1v 25hz output sample rate 10hz output sample rate 1hz output sample rate temperature (c) ?50 1 average power dissipation (w) 10 100 1000 10000 ?25 0 25 50 2451 g12 75 100
ltc2451 6 2451fg temperature (c) ?45 38 40 44 15 55 2451 g15 36 34 ?25 ?5 35 75 95 32 30 42 conversion time (ms) v cc = 5.5v, 4.1v, 2.7v temperature (c) ?45 19 20 22 15 55 2451 g16 18 17 ?25 ?5 35 75 95 16 15 21 conversion time (ms) v cc = 5.5v, 4.1v, 2.7v conversion period vs temperature 30hz mode typical performance characteristics t a = 25c; graphs apply to both 30hz and 60hz modes, unless otherwise noted. average power dissipation vs temperature v cc = 3v, 60hz mode power supply rejection vs frequency at v cc conversion period vs temperature 60hz mode temperature (c) ?50 1 average power dissipation (w) 10 100 1000 10000 ?25 0 25 50 2451 g13 75 100 25hz output sample rate 10hz output sample rate 1hz output sample rate frequency at v cc (hz) 1 10 ?120 rejectioin (db) ?80 0 100 10k 100k 2451 g14 ?100 ?40 ?20 ?60 1k 1m 10m 30hz mode, 60hz mode
ltc2451 7 2451fg pin functions gnd (pin 1, 5): ground. connect to a ground plane through a low impedance connection. ref C (pin 2), ref + (pin 3): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , remains more positive than the negative reference input, ref C , by at least 2.5v. the differential reference voltage (v ref = ref + to ref C ) sets the full-scale range. v cc (pin 4): positive supply voltage. bypass to gnd (pin 1) with a 10f capacitor in parallel with a low series inductance 0.1f capacitor located as close to the part as possible. in (pin 6): analog input. ins single-ended input range is v ref C to v ref + . scl (pin 7): serial clock input of the i 2 c interface. the ltc2451 can only act as a slave and the scl pin only accepts an external serial clock. data is shifted into the sda pin on the rising edges of scl and output through the sda pin on the falling edges of scl. sda (pin 8): bidirectional serial data line of the i 2 c in - terface. the conversion result is output through the sda pin. the pin is high impedance unless the ltc2451 is in the data output mode. while the ltc2451 is in the data output mode, sda is an open-drain pull-down (which requires an external 1.7k pull-up resistor to v cc ). exposed pad (pin 9): ground. must be soldered to pcb ground. block diagram 16-bit ? a/d converter scl ref + v cc ref ? in sda 2451 bd i 2 c interface internal oscillator 3 4 7 8 gnd 1, 5, 9 1 2 6
ltc2451 8 2451fg applications information converter operation converter operation cycle the ltc2451 is a low power, delta-sigma analog-to- digital converter with an i 2 c interface. its operation, as shown in figure 1, is composed of three successive states: conversion, sleep, and data input/output. initially, at power-up, the ltc2451 is set to its default 60hz mode and performs a conversion. once the conversion is complete, the device enters the sleep state. while in the sleep state, power consumption is reduced by several orders of magnitude. the part remains in the sleep state as long it is not addressed for a read or write operation. the conversion result is held indefnitely in a static shift register while the part is in the sleep state. the device will not acknowledge an external request dur - ing the conversion state. after a conversion is fnished, the device is ready to accept a read/write request. the ltc2451s address is hard wired at 0010100. once the ltc2451 is addressed for a read operation, the device begins outputting the conversion result under the control of the serial clock (scl). there is no latency in the conver - sion result. the data output is 16 bits long and outputs from msb to lsb. data is updated on the falling edges of scl, allowing the user to reliably latch data on the rising edge of scl. in write operation, the device accepts one confguration byte and the data is shifted in on the rising edges of scl. a new conversion is initiated by a stop condition following a valid read or write operation, or by the conclusion of a complete read cycle (all 16 bits read out of the device). power-up sequence when the power supply voltage, v cc , applied to the con- verter is below approximately 2.1v, the adc performs a power-on reset. this feature guarantees the integrity of the conversion result. when v cc rises above this threshold, the converter generates an internal power-on reset (por) signal for approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2451 starts a conversion cycle and follows the succession of states described in figure 1. the frst conversion result follow - ing por is accurate within the specifcations of the device if the power supply voltage, v cc , is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. ease of use the ltc2451 data output has no latency, flter settling delay, or redundant results associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog input voltages requires no special actions. in the 30hz mode, the ltc2451 performs offset calibrations during every conversion. this calibration is transparent to the user and has no effect upon the cyclic operation previ - ously described. the advantage of continuous calibration is stability of the adc performance with respect to time and temperature. the ltc2451 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. this allows external flter networks to interface directly to the ltc2451. since the average input sampling current is 50na, an external rc lowpass flter using a 1k and 0.1f results in less than 1lsb additional error. figure 1. state diagram read/write acknowledge data input/output yes yes 2451 f01 stop or read 16 bits sleep conversion power-on reset no no
ltc2451 9 2451fg applications information v cc power should not be removed from the device when t he i 2 c bus is active to avoid loading the i 2 c bus lines through the internal esd protection diodes. each device on the i 2 c bus is recognized by a unique address stored in that device and can operate either as a transmitter or receiver, depending on the function of the device. in addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers. a master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. devices addressed by the master are considered a slave. the address of the ltc2451 is 0010100. the ltc2451 can only be addressed as a slave. it can only transmit the last conversion result. the serial clock line, scl, is always an input to the ltc2451 and the serial data line, sda, is bidirectional. figure 2 shows the defnition of the i 2 c timing. the start and stop conditions a start (s) condition is generated by transitioning sda from high to low while scl is high. the bus is consid - ered to be busy after the start condition. when the data transfer is fnished, a stop (p) condition is generated by transitioning sda from low to high while scl is pulled high. the bus is free after a stop is generated. start and stop conditions are always generated by the master. when the bus is in use, it stays busy if a repeated start (sr) is generated instead of a stop condition. the re - peated start (sr) conditions are functionally identical to the start (s). reference voltage range this converter accepts a truly differential external reference voltage. the voltage range for the ref + and ref C pins covers the entire operating range of the device (gnd to v cc ). for correct converter operation, v ref + C v ref C 2.5v. the ltc2451 differential reference input range is 2.5v to v cc . for the simplest operation, ref + can be shorted to v cc and ref C can be shorted to gnd. input voltage range ignoring offset and full-scale errors, the converter will theoretically output an all zero digital result when the input is at v ref C (a zero scale input) and an all one digital result when the input is at v ref + (a full-scale input). in an underrange condition, for all input voltages less than the voltage corresponding to output code 0, the converter will generate the output code 0. in an overrange condition, for all input voltages greater than the voltage correspond - ing to output code 65535, the converter will generate the output code 65535. i 2 c interface the ltc2451 communicates through an i 2 c interface. the i 2 c interface is a 2-wire open-drain interface supporting multiple devices and masters on a single bus. the con - nected devices can only pull the data line (sda) low and never drive it high. sda is externally connected to the supply through a pull-up resistor. when the data line is free, it is pulled high through this resistor. data on the i 2 c bus can be transferred at rates up to 100k/s in the standard mode and up to 400k/s in the fast mode. the figure 2. defnition of timing for fast/standard mode devices on the i 2 c bus sda scl s sr p s t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf t r t f t r t f t high 2451 f02
ltc2451 10 2451fg data tra nsferring after the start condition, the i 2 c bus is busy and data transfer can begin between the master and the addressed slave. data is transferred over the bus in groups of nine bits, one byte followed by one acknowledge (ack) bit. the master releases the sda line during the ninth scl clock cycle. the slave device can issue an ack by pulling sda low or issue a not-acknowledge (nack) by leaving the sda line high impedance (the external pull-up resistor will hold the line high). change of data only occurs while the clock line (scl) is low. data format after a start condition, the master sends a 7-bit address (factory set at 0010100), followed by a read request (r) or write request (w) bit. the bit r is 1 for a read request and 0 for a write request. if the 7-bit address agrees with the ltc2451s address, the device is selected. when the device is addressed during the conversion state, it does not accept the request and issues a nack by leaving the sda line high. if the conversion is complete, the ltc2451 issues an ack by pulling the sda line low. the user can send one byte of data into the ltc2451 fol - lowing a write request and an ack. the sequence is shown in figure 3. the write sequence is used solely to set the conversion speed. the default conversion speed is 60hz. the user can specify a 30hz conversion speed by setting the eighth bit (s30) = 1, or specify a 60hz conversion speed by setting the eighth bit (s30) = 0. after a read request and an ack, the ltc2451 can output data, as shown in figure 4. the data output stream is 16 bits long and is shifted out on the falling edges of scl . applications information figure 3. timing diagram for write sequence figure 4. timing diagram for read sequence 1 7 8 9 2 3 1 4 s30 w sda scl 7-bit address start by master s30 = 1: 30hz mode s30 = 0: 60hz mode 5 6 7 8 9 ack by ltc2451 sleep data input 2451 f03 ack by master 1 7 8 9 2 3 1 8 d8 d13 d14 msb d15 r sda scl 7-bit address start by master d7 d6 d5 d0 lsb 9 1 2 3 8 9 ack by ltc2451 ack by master nack by master sleep data output convert 2451 f04
ltc2451 11 2451fg the frst bit is the msb (d15) and is followed by succes - sively less signifcant bits (d14, d13 ...) until the lsb (d0) is output by the ltc2451. this sequence is summarized in figure 5. operation sequence continuous read conversions from the ltc2451 can be continuously read (see figure 7). at the end of a read operation, a new conversion automatically begins. at the conclusion of the conversion cycle, the next result may be read using the method described above. if the conversion cycle is not concluded and a valid address selects the device, the ltc2451 generates a nack signal indicating the conver - sion cycle is in progress. continuous read/write once the conversion cycle is concluded, the ltc2451 can be written to, and then read from, using the repeated start (sr) command. figure 7 shows a cycle which begins with a data write, a repeated start, followed by a read, and concluded with a stop command. the following conversion begins after all 16 bits are read out of the device, or after the stop com- mand, and uses the newly programmed confguration. applications information figure 5. conversion sequence sleep 7-bit address (0010100) s p r ack read data output conversion conversion 2451 f05 figure 7. write, read, start conversion figure 6. consecutive reading at the same confguration sleep 7-bit address (0010100) s p p r ack read data output conversion conversion 2451 f06 sleep 7-bit address (0010100) s p r ack read dataoutput conversion sleep 7-bit address (0010100) 7-bit address (0010100) s r sr w ack write data output data input address conversion conversion 2451 f07 p ack read
ltc2451 12 2451fg discarding a conversion result and initiating a new conversion with optional confguration updating at the conclusion of a conversion cycle, a write cycle can be initiated. once the write cycle is acknowledged, a stop (p) command initiates a new conversion. if a new confguration is required, this data can be written into the device and a stop command initiates a new conversion (see figure 8). synchronizing the ltc2451 with the global address call the ltc2451 can also be synchronized with the global address call (see figure 9). to achieve this, the ltc2451 must frst have completed the conversion cycle. the master issues a start, followed by the ltc2451 global address 1110111, and a write request. the ltc2451 will be selected and acknowledge the request. if desired, the master then sends the write byte to program the 30hz or 60hz mode. after the optional write byte, the master ends the write operation with a stop. this will update the confguration registers (if a write byte was sent) and initiate a new conversion on the ltc2451, as shown in figure 9. in order to synchronize the start of the conver - sion without affecting the confguration registers, the write operation can be aborted with a stop. this initiates a new conversion on the ltc2451 without changing the confguration registers. preserving the converter accuracy the ltc2451 is designed to dramatically reduce the conver - sion results sensitivity to device decoupling, pcb layout, antialiasing circuits, line and frequency perturbations. nevertheless, in order to preserve the high accuracy capa - bility of this part, some simple precautions are desirable. digital signal levels due to the nature of cmos logic, it is advisable to keep input digital signals near gnd or v cc . voltages in the range of 0.5v to v cc C 0.5v may result in additional cur - rent leakage from the part. driving v cc and gnd in relation to the v cc and gnd pins, the ltc2451 com - bines internal high frequency decoupling with damping elements, which reduce the adc performance sensitivity to pcb layout and external components. nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling. a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the v cc and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc. figure 8. start a new conversion without reading old conversion result applications information figure 9. synchronize the ltc2451 with the global address call sleep 7-bit address (0010100) write (optional) s p w ack data input conversion conversion 2451 f08 global address (1110111) sleep conversion s w ack write (optional) p 2451 f09 data input
ltc2451 13 2451fg it is also desirable to avoid any via in the circuit path, starting from the converter v cc pin, passing through these two decoupling capacitors, and returning to the converter gnd pin. the area encompassed by this circuit path, as well as the path length, should be minimized. very low impedance ground and power planes, and star connections at both v cc and gnd pins, are preferable. the v cc pin should have three distinct connections: the frst to the decoupling capacitors described above, the second to the ground return for the input signal source, and the third to the ground return for the power supply voltage source. driving ref + and ref C a simplifed equivalent circuit for ref + and ref C is shown in figure 10. like all other a/d converters, the ltc2451 is only as accurate as the reference it is using. therefore, it is important to keep the reference line quiet by careful low and high frequency power supply decoupling. the lt6660 reference is an ideal match for driving the ltc2451s ref + pin. the ltc6660 is available in a 2mm 2mm dfn package with 2.5v, 3v, 3.3v and 5v options. figure 10. ltc2451 analog input and reference pins equivalent circuit a 0.1f, high quality, ceramic capacitor in parallel with a 10f ceramic capacitor should be connected between the ref + /ref C and gnd pins, as close as possible to the package. the 0.1f capacitor should be placed closest to the adc. driving in the input drive requirements can best be analyzed using the equivalent circuit of figure 11. the input signal, v sig , is connected to the adc input pin (in) through an equivalent source resistance r s . this resistor includes both the actual generator source resistance and any additional optional resistors connected to the input pin. an optional input capacitor, c in , is also connected between the adc input pin and gnd. this capacitor is placed in parallel with the adc input parasitic capacitance, c par . depending on the pcb layout, c par has typical values between 2pf and 15pf. in addition, the equivalent circuit of figure 11 includes the converter equivalent internal resistor, r sw , and sampling capacitor, c eq . applications information v cc v cc v cc c eq 0.35pf (typ) ref + in ref ? 2451 f10 r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak r sw 15k (typ) i leak i leak figure 11. ltc2451 input drive equivalent circuit v sig 2451 f11 i leak i leak r sw 15k (typ) i conv c in in v cc r s c eq 0.35pf (typ) c par + ?
ltc2451 14 2451fg there are some immediate trade-offs in r s and c in without needing a full circuit analysis. increasing r s and c in can provide the following benefts: 1. due to the ltc2451s input sampling algorithm, the input current drawn by the input pin (in) over a con - version cycle is 50na. a high r s ? c in attenuates the high frequency components of the input current, and r s values up to 1k result in <1lsb additional inl. 2. the bandwidth from v sig is reduced at the input pin. this bandwidth reduction isolates the adc from high frequency signals, and as such provides simple anti - aliasing and input noise reduction. 3. switching transients generated by the adc are attenu - ated before they go back to the signal source. 4. a large c in gives a better ac ground at the input pin, helping reduce refections back to the signal source. 5. increasing r s protects the adc by limiting the current during an outside-the-rails fault condition. there is a limit to how large r s ? c in should be for a given application. increasing r s beyond a given point increases figure 12. measured inl vs input voltage, c in = 0.1f, v cc = 5v, t a = 25c the voltage drop across r s due to the input current, to the point that signifcant measurement errors exist. additionally, for some applications, increasing the r s ? c in product too much may unacceptably attenuate the signal at frequencies of interest. for most applications, it is desirable to implement c in as a high quality 0.1f ceramic capacitor and r s 1k. this capacitor should be located as close as possible to the input pin. furthermore, the area encompassed by this circuit path, as well as the path length, should be minimized. in the case of a 2-wire sensor that is not remotely grounded, it is desirable to split r s and place series resistors in the adc input line and in the sensor ground return line, which should be tied to the adc gnd pin using a star connection topology. figure 12 shows the measured ltc2451 inl versus the input voltage as a function of r s value with an input ca - pacitor c in = 0.1f. in some cases, r s can be increased above these guide - lines. the input current is negligible when the adc is applications information input voltage (v) 0 inl(lsb) ?4 0 4 3 5 2451 f12 ?8 ?12 ?16 1 2 4 8 12 16 r s = 10k r s = 1k r s = 0
ltc2451 15 2451fg figure 13. measured inl vs input voltage, c in = 0, v cc = 5v, t a = 25c figure 14. ltc2451 input signal attenuation vs frequency either in sleep or i/o modes. thus, if the time constant of th e input rc circuit t = r s ? c in , is of the same order of magnitude or longer than the time periods between actual conversions, then one can consider the input current to be reduced correspondingly. these considerations need to be balanced out by the input signal bandwidth. the 3db bandwidth 1/(2 p r s c in ). finally, if the recommended choice for c in is unac - ceptable for the users specifc application, an alternate strategy is to eliminate c in and minimize c par and r s . in practical terms, this confguration corresponds to a low impedance sensor directly connected to the adc through minimum length traces. actual applications include current measurements through low value sense resistors, temperature measurements, low impedance voltage source monitoring, and so on. the resultant inl versus v in is shown in figure 13. the measurements of fig ure 13 include a capacitor c par corresponding to a minimum sized layout pad and a minimum width input trace of about 1" length. signal bandwidth and noise equivalent input bandwidth the ltc2451 includes a sinc 1 type digital flter with the frst notch located at f 0 = 60hz. as such, the 3db input signal bandwidth is 26.54hz. the calculated ltc2451 input signal atte nuation versus frequency over a wide frequency range is shown in figure 14. the calculated ltc2451 input signal attenuation with low frequencies is shown in figure 15. the converter noise level is about 1.4v rms , and can be modeled by a white noise source connected at the input of a noise-free converter. applications information input signal attenuation (db) ?40 0 2451 f14 ?60 ?80 ?20 ?100 input signal frequency (mhz) 0 1.00 1.25 1.50 2.5 5.0 7.5 input voltage (v) 0 inl (lsb) 8 6 4 2 0 ?2 ?4 ?6 ?8 4 2451 f13 1 2 3 5 3.5 0.5 1.5 2.5 4.5 r s = 1k r s = 10k r s = 0
ltc2451 16 2451fg typical applications easy passive input easy active input ltc2451 100nf preconditioned sensor with voltage output 1k v+ gnd v out 2451 ta02 ltc2451 100nf r s < 1k 2451 ta03 figure 15. ltc2451 input signal attenuation vs frequency (low frequencies) input signal frequency (hz) 0 input signal attenuatioin (db) ?20 ?10 0 480 2451 f15 ?30 ?40 ?25 ?15 ?5 ?35 ?45 ?50 120 60 240 180 360 420 540 300 600 for a simple system noise analysis, the input drive cir - cuit can be modeled as a single-pole equivalent circuit characterized by a pole location, f i , and a noise spectral density, n i . if the converter has an unlimited bandwidth, or at least a bandwidth substantially larger than f i , then the total noise contribution of the external drive circuit would be: v n = n i p / 2 ? f i the total system noise level can then be estimated as the square root of the sum of (v n 2 ) and the square of the ltc2451 noise foor (~2v 2 ). applications information
ltc2451 17 2451fg ddb package 8-lead plastic dfn (3mm 2mm) (reference ltc dwg # 05-08-1702 rev b) 2.00 0.10 (2 sides) note: 1. drawing conforms to version (wecd-1) in jedec package outline m0-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.56 0.05 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 2.15 0.05 (2 sides) 3.00 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0 ? 0.05 (ddb8) dfn 0905 rev b 0.25 0.05 0.50 bsc pin 1 r = 0.20 or 0.25 45 chamfer 0.25 0.05 2.20 0.05 (2 sides) recommended solder pad pitch and dimensions 0.61 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.50 bsc package description
ltc2451 18 2451fg package description ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637) 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0802 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.52 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref
ltc2451 19 2451fg information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number f 6/10 added text to i 2 c interface section 9 g 10/10 revised ts8 package part numbers in order information section 2 (revision history begins at rev f)
ltc2451 20 2451fg linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2008 lt 1110 rev g ? printed in usa related parts part number description comments lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/c drift lt1790 micropower precision reference in tsot-23-6 package 60a max supply current, 10ppm/c max drift, 1.25v, 2.048v, 2.5v, 3v, 3.3v, 4.096v and 5v options ltc1860/ltc1861 12-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1860l/ltc1861l 12-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc1864/ltc1865 16-bit, 5v, 1-/2-channel 250ksps sar adc in msop 850a at 250ksps, 2a at 1ksps, so-8 and msop packages ltc1864l/ltc1865l 16-bit, 3v, 1-/2-channel 150ksps sar adc 450a at 150ksps, 10a at 1ksps, so-8 and msop packages ltc2440 24-bit no latency ? tm adc 200nv rms noise, 8khz output rate, 15ppm inl ltc2480 16-bit, differential input, no latency ? adc, with pga, temperature sensor, spi easy drive tm input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2481 16-bit, differential input, no latency ? adc, with pga, temperature sensor, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2482 16-bit, differential input, no latency ? adc, spi easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2483 16-bit, differential input, no latency ? adc, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2484 24-bit, differential input, no latency ? adc, spi easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc2485 24-bit, differential input, no latency ? adc, i 2 c easy drive input current cancellation, 600nv rms noise, tiny 10-lead dfn package ltc6241 dual, 18mhz, low noise, rail-to-rail op amp 550nv p-p noise, 125v offset max lt6660 micropower references in 2mm 2mm dfn package, 2.5v, 3v, 3.3v, 5v 20ppm/c maximum drift, 0.2% max ltc2450 easy-to-use, ultra-tiny 16-bit adc 2lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 30hz output rate ltc2450-1 easy-to-use, ultra-tiny 16-bit adc 2lsb inl, 50na sleep current, tiny 2mm 2mm dfn-6 package, 60hz output rate ltc2453 i 2 c, differential, ultra-tiny 16-bit adc 2lsb inl, 50na sleep current, 3mm 2mm dfn-8 and tsot-8 packages, 60hz output rate typical application thermistor measurement scl sda thermistor 1k to 10k 10k 5k in ref + v cc ref ? gnd ltc2451 2451 ta04 100nf

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